To train students in the current technological topics on Integrated Circuits: design, fabrication and testing
PEO-3 To train students in Device fabrication in class 1000 & class 100 clean room
PEO-4 To offer training on full cycle development of Integrated circuits, Device design using Electronic Design Automation (EDA) tool.
PEO-4 To train the students in analytical reasoning, experimental skills and attitude to collaborate between inter-disciplinary research groups
Mapping Program Educational Objectives (PEOs)
with Mission Statements (MS)
| |
MS-1 |
MS-2 |
MS-3 |
MS-4 |
| PEO-1 |
3 |
3 |
3 |
3 |
| PEO-2 |
3 |
3 |
3 |
3 |
| PEO-3 |
2 |
3 |
3 |
3 |
| PEO-4 |
1 |
2 |
2 |
3 |
| PEO-5 |
2 |
3 |
2 |
2 |
Note: ‘3’ in the box for ‘high-level’mapping, 2 for ‘Medium-level’mapping, 1 for ‘Low-level’ mapping.
Name of the Centre: CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Program Outcomes (POs)
After completion of this M.Tech program, the students will be able to
PO-1 Develop scientific and engineering knowledge for design, prototype and testing of devices, Integrated Circuits and systems
PO-2 Collaboration, Teamwork and project management skills
PO-3 Critical thinking for analysis, problem solving and research
PO-4 Promote Entrepreneurship and professional ethics
PO-5 Original thinking, Creativity to solve complex systems and problem formulation
PO-6 Technical presentation and demonstration skills
Program Specific Outcomes (PSOs)
PSO-1 Design and develop efficient VLSI architectures to implement digital systems, signal processing algorithms and systems .
PSO-2: Design of analog, RF, mixed signal ASIC and systems leading to IC tape-out, test and measurement.
PSO-3: Design, simulate, fabricate and test microwave Integrated circuits, MEMS using EDA tool and design concepts.
PSO-4 Exposure to design, simulate and fabricate microelectronic devices
PSO-5 Identify techniques to improve the EDA tool to minimize design productivity gap.
Mapping of Program Outcomes (POs) and Program Specific Outcomes (PSOs) with Program Educational Objectives (PEOs)
| |
PEO-1 |
PEO-2 |
PEO-3 |
PEO-4 |
PEO-5 |
| PO-1 |
3 |
3 |
3 |
2 |
3 |
| PO-2 |
2 |
2 |
3 |
3 |
3 |
| PO-3 |
2 |
2 |
2 |
1 |
3 |
| PO-4 |
1 |
1 |
2 |
1 |
2 |
| PO-5 |
1 |
2 |
2 |
2 |
2 |
| PO-6 |
2 |
2 |
2 |
2 |
2 |
| PSO-1 |
3 |
1 |
3 |
3 |
3 |
| PSO-2 |
3 |
1 |
3 |
3 |
3 |
| PSO-3 |
1 |
3 |
3 |
3 |
3 |
| PSO-4 |
3 |
3 |
3 |
3 |
1 |
| PSO-5 |
2 |
2 |
3 |
3 |
2 |
Note: ‘3’ in the box for ‘high-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low-level’ mapping.
Syllabus Structure of M.Tech (Microelectronics & VLSI Design)
Semester –I No. of credits – 27
| Course No |
Title of the course |
No. of Contact Hours |
No. of Credits |
| MV401 |
Semiconductor Device Physics and Modelling |
4 |
4 |
| MV402 |
Analog and Mixed Signal IC Design |
4 |
4 |
| MV403 |
Digital VLSI System Design |
4 |
4 |
| MV404 |
RF Devices and Circuits |
4 |
4 |
| MV405 |
Numerical techniques for Microelectronics Simulation |
2 |
2 |
| MV406 |
Microelectronics Simulation Lab |
4 |
2 |
| MV407 |
IC Design Lab |
6 |
3 |
| MV408 |
RF IC Lab |
4 |
2 |
| MV409 |
Semester Project -I |
4 |
2 |
Semester –II No. of credits – 25
| Course No. |
Title of the course |
No. of Contact Hours |
No.of Credits |
| MV451 |
Digital IC Design |
4 |
4 |
| MV452 |
Nano Fabrication Lab |
8 |
4 |
|
Elective I |
4 |
4 |
|
Elective II |
4 |
4 |
|
Elective III |
4 |
4 |
| MV453 |
Semester Project -II |
6 |
3 |
| MV454 |
Seminar + Comprehensive Viva |
2 |
2 |
Semester –III No. of credits – 24
| Course No |
Title of the course |
No of Credits |
| MV501 |
Project work + seminar |
24 |
Semester –IV No. of credits – 24
| Course No |
Title of the course |
No of Credits |
| MV 501 |
Project work + Dissertation +Viva |
24 |
|
|
|
List of Electives: A student can choose three electives combining from Stream A and stream B, However, he/she need to choose minimum one from each stream. A particular elective will be offered depending on the available expertise and student group size (minimum number of 6 students are required to offer an elective)
Stream A:
| MV461: VLSI Test and Verification |
| MV462:VLSI CAD algorithms |
| MV463:Special Topics in Analog and Mixed Signal IC Design |
| MV464:Wireless Communication IC Design |
| MV465:VLSI Signal Processing |
| MV466:Microsystems Modeling and Design |
| MV474: High speed VLSI and system on chip: Design and implementation |
Stream B:
| MV467:Sensors, Science and Technology |
| MV468:Thin Film Technology |
| MV469:Advanced RF Devices and Circuits |
| MV470:III-V Compound Semiconductors |
| MV471:Nano Technology |
| MV472:MEMS and THz Technology |
| MV473:Optoelectronics |
Name of the Centre :CASEST
Name of the Academic Program : M.Tech (Microelectronics & VLSI Design)
Course Code: MV401
Title of the course: Semiconductor Device Physics and Modeling
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Discuss advanced physical concepts in Semiconductor Electronics such as carrier and impurity statistics, and hot carriers transport effects.
CO-2: Analyze electronic model for the charge distribution at a semiconductor interface as a function of the interface conditions
CO-3: Discuss the operation of several basic semiconductor devices: p-n junctions, metal-semiconductor junctions, Diodes, metal oxide semiconductor field effect transistors (MOSFETs), Complementary MOSFETs (CMOS).
CO-4 : Apply the concepts related to device physics and modelling to solve problems
CO 5: Design new problems related to device and modelling
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
3 |
3 |
1 |
3 |
2 |
3 |
2 |
1 |
3 |
3 |
| CO2 |
3 |
3 |
3 |
1 |
3 |
2 |
3 |
2 |
1 |
3 |
3 |
| CO3 |
3 |
3 |
3 |
1 |
3 |
2 |
3 |
2 |
1 |
3 |
3 |
| CO4 |
3 |
3 |
3 |
1 |
3 |
3 |
3 |
2 |
1 |
3 |
3 |
| CO5 |
3 |
3 |
3 |
1 |
3 |
3 |
3 |
2 |
1 |
3 |
3 |
Note: ‘3’ in the box for ‘High-level’mapping, 2 for ‘Medium-level’mapping, 1 for ‘Low’-level’mapping
Detailed Syllabus:
Unit I
Overview of Semiconductor Physics- Crystal Structure, Concepts of Band structure, Valence and Conduction bands and Electrons and Holes, Density of States, Carrier statistics, Equilibrium carrier concentrations in intrinsic and doped semi-conductors.
Carrier mobility and scattering mechanisms recombination / lifetime due to various mechanisms, determination of carrier mobilities and life times, photoconductivity.
Unit II
p-n junctions- Band structures across homogeneous junctions, depletion widths and capacitances of abrupt and linearly graded junctions, current flow through p –n junctions, ideal and practical I-V Characteristics, breakdown, heterogeneous junctions
Unit III
BJTs: current through a BJT, current gain and its dependence on various factors, Ebers-Moll and Gummel-Poon Models
Unit IV
Schottky junctions: Metal Semi-conductor junctions, determination of work-functions and barriers heights, Band structures across junctions, Schottky diode and its I-V Characteristics
Unit V
Unipolar devices: JFETs, MESFETs, MOS structures, Band Structure, CV curves, Strong inversion condition, MOSFET characteristics, depletion and enhancement structures, short-channel and hot-carrier effects, HEMT, HBT
Books:
Physics of Semi-conductor Devices- S.M. Sze
Semi-conductor Devices – Physics and technology – S. M. Sze
Name of the Centre :CASEST
Name of the Academic Program : M.Tech (Microelectronics & VLSI Design)
Course Code: MV402 Title of the Course: Analog and Mixed Signal IC Design
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course, the students will be able to
CO 1: Apply the knowledge of different biasing styles for different electronic circuits (Apply level)
CO 2: Design basic building blocks of analog ICs up to layout level.(Apply)
CO 3: Develop a procedure for optimal compensation of op-amp against
process, supply and temperature variations (Apply)
CO 4: Identify suitable topologies of the constituent sub-systems and
corresponding circuits as per the specifications of the system (Analyze)
CO 5: Design an optimally compensated Op-amp including parasitic effects up
to the tape-out (create level)
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
2 |
1 |
1 |
1 |
3 |
3 |
1 |
1 |
1 |
2 |
| CO2 |
3 |
3 |
3 |
1 |
3 |
3 |
3 |
2 |
3 |
3 |
2 |
| CO3 |
1 |
1 |
1 |
3 |
1 |
2 |
3 |
1 |
3 |
3 |
1 |
| CO4 |
1 |
1 |
3 |
3 |
1 |
3 |
3 |
1 |
3 |
2 |
1 |
| CO5 |
3 |
1 |
3 |
2 |
1 |
3 |
3 |
2 |
1 |
1 |
1 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Course Contents:
Unit-1: MOS Device Structure and Circuit Models, Single-Stage and Differential Amplifiers, Passive and Active Current Mirrors, single- & multi-stage amplifier design
Unit-2: Frequency Response of Amplifiers, Noise, Feedback, Op Amp Design, Stability and Frequency Compensation
Unit-3: Bandgap References, Introduction to Switched-Capacitor Circuits, Analog and Mixed Signal Layout Design Flow.
Unit-4: Introduction to Switched Capacitor Circuits, Sampling circuits and architecture Introduction to Data convertors, digital to analog conversion, analog to digital conversion and oversampled converters
=============================================================
Text books:
- B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
Reference books:
- P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, 2001, Wiley.
- D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.
- Synthesis and optimization of Digital Circuits by G. D. Michelli, Springer.
Name of the Centre: CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV403 Title of the Course: Digital VLSI System Design
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge: Nil
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Explain the principle and steps to implement Digital design on FPGA
CO-2: Design, and evaluate combinational and sequential digital sub blocks using different coding styles
CO-3 Analyze the role of different synthesis algorithms and approaches to Digital Design.
CO-4 Explain the semicustom and full custom design flow
CO-5 Build a system on chip solution for digital design using FPGA
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
2 |
1 |
1 |
1 |
3 |
3 |
1 |
1 |
1 |
2 |
| CO2 |
3 |
3 |
3 |
1 |
3 |
3 |
3 |
2 |
1 |
|
2 |
| CO3 |
1 |
3 |
3 |
1 |
3 |
2 |
3 |
|
1 |
|
1 |
| CO4 |
1 |
3 |
2 |
1 |
2 |
3 |
3 |
1 |
1 |
1 |
1 |
| CO5 |
3 |
3 |
1 |
2 |
3 |
3 |
3 |
2 |
1 |
|
1 |
Note: ‘3’ in the box for ‘High-level’mapping, 2 for ‘Medium-level’mapping, 1 for ‘Low’-level’mapping
Detailed Syllabus:
Unit -I Design styles of IC, VLSI Design flow, Introduction to FPGA, the need for a language to design digital circuits, Verilog language elements and data types. Structural style modelling, Data flow modeling, Behavioral modelling.
Unit-II: Combinational logic design, Sequential logic design, Arithmetic circuit design, Synthesis of RAM, ROM, FSM design, FSM Based Modeling of Digital Circuits,
Unit III: Logic synthesis: two level, multilevel, high level synthesis algorithms, Technology mapping, Timing analysis
Unit IV: Physical design: Floor planning, Placement, Cock tree synthesis, detailed routing, packaging, signoff. (Qualitative overview and problem formulation only)
Unit V: Introduction to embedded system design, system design methodologies, Introduction to System on Chip, System on chip design flow, Embedded processor architecture, Profiling approach, Hw-SW codesign.
Text books:
- Verilog Digital System Design RT Level Synthesis, Testbench and Verification by Z. Navabi, McGraw Hill (2005) ISBN-13: 978-0071445641
- Fundamentals of Digital Logic with Verilog Design, By Stephen Brown, Zvonko Vranesic Tata McGraw-Hill edition.
- Computer System Design System-on-Chip Michael J. Flynn Wayne Luk,published by Published by John Wiley & Sons (2011), ISBN 978-0-470-64336-5
Reference books:
- Embedded Core Design with FPGAs, Z. Navabi McGraw Hill (2007), ISBN 978-0-07-147481-8.
- Synthesis and optimization of Digital Circuits by G.D.Michelli, Springer.
Name of the Centre: CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV404 Title of the Course: RF/ Microwave ICs
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): The following courses at the B.Tech or M.Sc. level.
1. Electromagnetic Theory
- Advanced Mathematical Methods
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Analyze the difference between high frequency ICs and conventional ICs and apply transmission line and distributed element-based approaches to solve problems with high frequency circuits.
CO-2: Apply impedance matching techniques for different circuit conditions and frequency ranges. Use of Smith charts.
CO-3 Evaluate ways to miniaturize the high frequency passives, interconnects and active devices and also by multilayering.
CO-4 Analyze different types of planar transmission lines and their design considerations.
CO-5 Apply the design approach in planar circuits with filter as an example. (Lumped to distributed conversion).
CO-6 Apply softwares to achieve high frequency circuit design goals along with IC 407 course.
CO-7 Evaluate emerging high frequency miniaturization techniques through a Term Paper.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
1 |
3 |
3 |
2 |
3 |
1 |
2 |
3 |
1 |
3 |
| CO2 |
3 |
1 |
3 |
1 |
3 |
2 |
1 |
2 |
3 |
1 |
1 |
| CO3 |
3 |
1 |
3 |
3 |
3 |
1 |
1 |
2 |
3 |
1 |
3 |
| CO4 |
3 |
1 |
3 |
3 |
3 |
1 |
1 |
2 |
3 |
1 |
3 |
| CO5 |
3 |
3 |
3 |
3 |
3 |
2 |
1 |
2 |
3 |
1 |
3 |
| CO6 |
3 |
3 |
3 |
3 |
3 |
2 |
1 |
2 |
3 |
1 |
3 |
| CO7 |
3 |
3 |
3 |
3 |
3 |
3 |
1 |
2 |
3 |
1 |
3 |
Detailed Syllabus:
UNIT-1 High Frequency Electronics
Why RF communication? Unique features of RF communication. Lumped vs. Distributed approach. Why RF circuits are to be treated differently in both active and passive devices? How Miniaturization leads to higher frequency operation? Introduction to high frequency ICs. Challenges and ways to miniaturize a high frequency circuit. Hybrid and integrated approach. High frequency ICs with lumped elements. MIC, MMIC and RFICs. Low frequency vs. High frequency models and parameters.
UNIT-II Transmission Line Theory, Impedance Transformation and Matching
Review of EM Theory and Transmission lines. Impedance transformation and its effect on microwave circuits. Transmission line sections as circuit elements. Smith chart and admittance chart. Impedance matching techniques for narrow band and broadband operation. Impedance matching using T.line sections, quarter wave lines and lumped elements.
UNIT –III Planar Transmission Lines
Planar transmission lines that can be miniaturized: Striplines, Microstriplines, Coplanar waveguides. Design and analysis of microstrip and coplanar waveguide circuits. T.Line discontinuities as circuit elements.
UNIT –IV Materials, Fabrication and Miniaturization
Substrates for transmission lines – dielectrics vs semiconductors. Lumped L,C and R and their models. Parasitics in high frequency circuits and ways to model them.
Materials used for their realization and their properties: Substrates, conductors, semiconductors, dielectrics and magnetic materials. Micromachining for lumped elements and T.Lines, RF MEMS, Integrated inductors and surface integrated waveguides.
UNIT –V Microwave Filter Design, Realization and Testing.
Microwave filter design. Filters using transmission line sections. Kuroda’s Identities. Richard’s transformation. Microwave Resonators, Filters using resonators, Varactors and tuning techniques, on wafer probing and on wafer calibration techniques.
Text Books:
David M. Pozar, “Microwave Engineering,” 2nd Edition, John Wiley 1998, ISBN 0-471-17096-8.
Peter A. Rizzi, “Microwave Engineering – Passive Circuits”, PHI, ISBN 81-203-1461-1
RFIC and MMIC design and technology, I.D. Robertson and S.Lucyszyn, IEE Circuits, Devices and Systems Series 13. ISBN-10 : 0852967861
Related IEEE Journal Papers
Reference Books:
K. C. Gupta, Ramesh Garg, Inder Bahl, and Prakash Bhartia, “Microstrip Lines and Slotlines,” Artech House, 2nd edition, 1996, ISBN: 089006766X.
T. C. Edwards and M. B. Steer, “Foundations of Interconnect and Microstrip Design,” John Wiley & Sons, 3rd edition, 2001, ISBN: 0471607010.
Mike Golio (Ed.), The RF and Microwave Handbook, CRC Press. ISBN: 9780849385926.
Novel technologies for microwave and millimeter-wave applications, Jean-Fu Kiang, Kluwer Academic Publishers. ISBN -10: 1441954015.
Name of the Centre: CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV405:
Title of the Course: Numerical techniques for Microelectronics Simulation
L-T-P: 2-0-0 Credits: 2
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO1: Recognize the procedure to solve non-linear algebraic problem which is employed for the interpretation of electrostatic potential of the device.
CO2: Describe the flow of carrier densities in semiconductor device and briefly review the non-linear iteration solution method used in numerical simulation.
CO3: Identify the carrier mobility along with scattering effect and growth of oxide layer on the material surface.
CO4: Examine the integrity of circuit design and predict the circuit behaviour.
CO5: Illustrate the circuits in terms of DC, AC, noise, distortion etc at simulation level.
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
1 |
3 |
|
1 |
|
|
|
3 |
2 |
3 |
| CO2 |
3 |
1 |
3 |
|
1 |
|
|
|
3 |
2 |
3 |
| CO3 |
2 |
|
2 |
|
1 |
|
|
|
3 |
2 |
3 |
| CO4 |
2 |
|
3 |
|
1 |
|
|
|
3 |
2 |
2 |
| CO5 |
2 |
|
3 |
|
1 |
|
|
|
3 |
2 |
3 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Module-I: Numerical Analysis Review: Direct solution methods of partial differential equations, Iterative solution methods of partial differential equations.
Module –II: Drift-Diffusion Model: Physical limitations, Modeling of Continuity equation, Bipolar semiconductor equations, Normalization and scaling, Gummel’s iteration method, Newton’s method, Time-dependent simulations, Examples of Application of DD model.
Module – III: Mobility models used in commercial simulators. Models for thermal oxidation (dry and wet).
Module IV: Introduction to SPICE modeling, modeling of elements (like resistor, capacitor, inductor, diode, BJT, JFET, MOS capacitor and MOSFET). Introduction to setting model parameters, parameter extraction and model validation. Overview of BSIM and EKV model for MOSFETs.
Module V: Circuit simulation techniques, DC analysis, AC analysis, transient analysis, SPICE Modeling of Process Variation, Process corners, Monte Carlo simulation, and sensitivity/worst case analysis, Simulation of digital and analog circuits, transfer function, frequency response, Noise analysis, distortion and spectral analysis, Basics of Finite element Analysis (FEA) and FDTD methods.
Reference books
1.Y. Tsividis, “Operation and modeling of MOS transistors”,2 nd Edition, McGraw-Hill, 1999.
2. Paul W. Tuinenga, “SPICE: A Guide to Circuit Simulation and Analysis Using PSpice”, 3 rd Edition, Pearson, 2006.
3. Paolo Antognetti and Giuseppe Massobrio, “Semiconductor Device Modeling with SPICE”, 2nd Edition, Tata McGraw-Hill, 2010.
4. BSIM Model (http://www-device.eecs.berkeley.edu/bsim/)
5. EKV Model (http://ekv.epfl.ch/)
Name of the Centre: CASEST
Name of the Academic Program M.Tech (IC Technology)
Course Code: MV406 , Title of the Course : Microelectronics Simulation Laboratory
L-T-P: 1-0-3 Credits: 2
Prerequisite Course / Knowledge (If any): Basics of semiconductor devices and methods of fabrication, at BTech level.
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Test discrete semiconductor devices using an industry standard method, analyse and interpret results.
CO-2: Explain the concepts of various device simulation program.
CO-3: Simulate device and circuit performance: Application, validation and
interpretation of results.
CO-4: Evaluate the performance of various semiconductor devices and
Circuits.
CO-5: Communicate the results of all experiments in the form of a written
technical report.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
2 |
3 |
1 |
3 |
2 |
0 |
1 |
0 |
3 |
1 |
| CO2 |
3 |
3 |
3 |
2 |
3 |
3 |
0 |
2 |
0 |
3 |
3 |
| CO3 |
3 |
3 |
3 |
3 |
3 |
3 |
0 |
2 |
0 |
3 |
3 |
| CO4 |
3 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
2 |
2 |
| CO5 |
2 |
3 |
1 |
1 |
1 |
3 |
0 |
0 |
0 |
2 |
1 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping.
Detailed Syllabus:
- Device characterization using Device Analyser.
- Process Simulation-(ion implantation, diffusion, oxidation).
- Device Simulation- (p-n Diode, Schottky diode, MOSFET).
- Circuit Simulation- (MOSFET based circuits).
Text books:
- “Semiconductor Material and Device Characterization” by Dieter K. Schroder (Wiley-IEEE Press; 3 edition (2015))
- Science and engineering of microelectronic Fabrication by Stephen CampbellOxford (University Press; Second edition (2012))
- VLSI Technology, S.M.Sze(McGraw Hill Education; 2 edition (2017))
Name of the Centre: CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV407 Title of the Course: IC Design Laboratory
L-T-P: 0+0-6 Credits: 3
Prerequisite Course / Knowledge (If any): MV402 and MV451 courses
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Design and verify the functionality of combinational and sequential circuits using Verilog HDL.
CO2: Implement and carry-out on chip debugging of the digital design on FPGA.
CO3: Design and simulate the basic analog integrated circuits like CMOS amplifiers and biasing circuits.
CO4: Design of integrated circuits for target specifications and checking the robustness of the design at different process corners
CO5: Implement physical design of integrated circuits, DRC and LVS check, post-layout extracted simulation.
CO6: Communicate the results of the experiment in the form of written technical report.
Mapping of Course Outcomes (Cos) with Program Outcomes (Pos)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
3 |
2 |
– |
2 |
2 |
3 |
2 |
2 |
3 |
2 |
| CO2 |
2 |
3 |
2 |
– |
2 |
2 |
3 |
2 |
2 |
2 |
2 |
| CO3 |
2 |
3 |
2 |
2 |
2 |
2 |
3 |
2 |
3 |
2 |
2 |
| CO4 |
2 |
3 |
2 |
2 |
3 |
2 |
3 |
2 |
3 |
2 |
3 |
| CO5 |
2 |
2 |
2 |
2 |
3 |
2 |
2 |
2 |
2 |
2 |
3 |
| CO6 |
3 |
2 |
2 |
3 |
2 |
3 |
2 |
2 |
2 |
2 |
2 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed syllabus:
List of experiments and mini-projects
1: Vivado Design Flow
2: Synthesizing a RTL Design
3: Implementing the Design
4: Using the IP Catalog and IP Integrator
5: Hardware Debugging
6: Analog and Mixed Signal IC Design Lab Projects
- CS and CG amplifiers with different loads, e.g., resistive, diode connected, current source
- Current mirrors, e.g., basic current mirror, cascode current mirror
- Differential amplifier
- Operational Transconductance amplifiers
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV 408 Title of the Course: RF IC Laboratory
L-T-P: 0-0-4 Credits: 2
Prerequisite Course / Knowledge (If any): It is the Lab component of the IC403 RF/Microwave ICs Course.
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Apply microwave measurement techniques using advanced measurement facilities like VNA.
CO-2: Apply the usage of EDA tools in doing high frequency circuit Design and Simulation.
CO-3 Apply EDA tools to Design and Simulate passive MIC circuits and active microwave circuits.
CO-4 Apply EDA tools for doing Full wave simulations by Method of Moments, FEM and FDTD.
CO-5 Analyze EDA tools to do Fullwave simulation and analysis of layout of high frequency circuits.
CO-6 Create high frequency circuits using EDA tools and simulate them.
CO-7 Fabricate the high frequency circuits.
CO-8 Communicate the results of these experiments in the form of a written technical report.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
2 |
3 |
3 |
3 |
3 |
1 |
2 |
3 |
1 |
3 |
| CO2 |
3 |
3 |
3 |
3 |
3 |
3 |
1 |
2 |
3 |
1 |
1 |
| CO3 |
3 |
3 |
3 |
3 |
3 |
3 |
1 |
2 |
3 |
1 |
3 |
| CO4 |
3 |
3 |
3 |
3 |
3 |
3 |
1 |
2 |
3 |
1 |
3 |
| CO5 |
3 |
3 |
3 |
3 |
3 |
2 |
1 |
2 |
3 |
1 |
3 |
| CO6 |
3 |
3 |
3 |
3 |
3 |
3 |
1 |
2 |
3 |
1 |
3 |
| CO7 |
3 |
3 |
3 |
3 |
3 |
3 |
1 |
2 |
3 |
1 |
3 |
| CO8 |
3 |
1 |
1 |
3 |
1 |
3 |
1 |
2 |
3 |
1 |
3 |
List of experiments/ Mini -projects
- Microwave measurement techniques for devices and circuits with Vector Network Analyzer, Power Meter and On Wafer Probing System.
- Tools for high frequency design, Familiarization of EDA tools for RF/ Microwave IC design and simulation, Usage of Models and Libraries for EDA tools, Design Examples (using both active and passive devices).
- Fullwave analysis in simulation and analysis of circuit layouts and housings using Method of Moments, FEM and FDTD.
- Design and simulation of active and passive microwave integrated circuits using EDA tools.
-
- The list of passive circuits includes: Dividers, Filters, Couplers, Tees, Circulators etc
- The list of active circuits includes: Amplifiers, oscillators, switches, phase shifters, mixers etc
- Design and Simulation of some of the above circuits/ devices will be done in the classes and remaining to be done as assignments.
- Fabrication and characterization of at least one of the above devices (in project mode. Extending to Semester break).
References:
- Practical RF Circuit Design for Modern Wireless Systems: Active Circuits and Systems Vol I and II, Les Besser and Rowan Gilmore. Artech House, ISBN-10: 1580535224
- RF circuit design, by Christopher Bowick, Elsevier. ISBN-10: 0750685182
- Reading Material provided by the EDA tool used.
4. 100 ADS Design Examples: Based on the Textbook: RF and Microwave Circuit Design, Ali A. Behagi, ISBN-10: 0996446621, Techno Search.
5. Related IEEE Papers.
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV409 Title of the Course: Semester Project-I
L-T-P: 0-0-4 Credits: 2
Prerequisite Course / Knowledge (If any): MV402 and MV451
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Design of one of the most widely used analog and mixed-signal IC building block such as op-amp, ADC, DAC, PLL, DLL, LNA etc.
CO2: Implement the selected building block for manufacturability by performing the checks such as PVT simulations, Monte-Carlo simulation etc.,
CO3: Design and simulate of layout, post-layout simulation, floor-planning etc.,
CO4: Project management, tapeout of the IC in a target technology
CO5: Verify by the building block by test and measurement of the IC
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
3 |
2 |
– |
2 |
2 |
3 |
2 |
3 |
2 |
3 |
| CO2 |
2 |
3 |
2 |
– |
2 |
2 |
2 |
3 |
3 |
2 |
3 |
| CO3 |
2 |
3 |
2 |
– |
2 |
3 |
2 |
3 |
3 |
2 |
3 |
| CO4 |
2 |
3 |
2 |
– |
2 |
3 |
2 |
3 |
3 |
2 |
2 |
| CO5 |
3 |
2 |
3 |
2 |
3 |
2 |
– |
2 |
2 |
3 |
3 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed syllabus:
Project: Design of one of the most widely used analog and mixed-signal IC building block such as op-amp, ADC, DAC, PLL, DLL, LNA. Design starts from specifications, followed simulation at the circuit level and layout level, and ends by test and measurement.
Name of the Centre: CASEST
Course Code: MV451 Title of the Course: Digital IC Design
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course, the students will be able to
CO1 Design CMOS inverters with specified noise margin and propagation delay.
CO2 Implement efficient techniques at circuit level for improving power and
speed of digital circuits
CO3 Identify sources of power consumption in a given VLSI Circuit
CO4 Estimate dynamic and leakage power components in a DSM
VLSI circuit
CO5 Analyze the dynamic and leakage power components in a DSM
VLSI circuit
CO6 Estimate power consumption at different levels of abstraction in a VLSI
system.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
3 |
2 |
3 |
1 |
3 |
3 |
3 |
3 |
3 |
2 |
| CO2 |
2 |
3 |
1 |
2 |
3 |
3 |
3 |
3 |
2 |
3 |
1 |
| CO3 |
3 |
3 |
1 |
3 |
3 |
2 |
3 |
2 |
3 |
3 |
1 |
| CO4 |
3 |
3 |
2 |
3 |
2 |
3 |
3 |
3 |
3 |
3 |
2 |
| CO5 |
3 |
3 |
1 |
2 |
3 |
3 |
3 |
2 |
1 |
1 |
1 |
| C06 |
1 |
3 |
3 |
2 |
3 |
2 |
3 |
2 |
3 |
3 |
1 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Unit-1: INTRODUCTION: A Historical Perspective; Issues in Digital Integrated Circuit Design; Quality Metrics of a Digital Design; Cost of an Integrated Circuit; Functionality and Robustness; Performance; Power and Energy Consumption; A Word on Process Variations; Perspective: Technology Scaling, More than Moore, New Technologies like: FDSOI, FINFET, 3D IC’s. etc., Interconnect Parameters — Capacitance, Resistance, and Inductance; Electrical Wire Models; The Ideal Wire; The Lumped Model; The Lumped RC model; The Distributed rc Line; The Transmission Line; SPICE Wire Models; Distributed rc Lines in SPICE; Transmission Line Models in SPICE.
Unit-2: THE CMOS INVERTER: The Static CMOS Inverter — An Intuitive Perspective; Evaluating the Robustness of the CMOS Inverter: The Static Behaviour; Switching Threshold; Noise Margins; Robustness Revisited; Performance of CMOS Inverter: The Dynamic Behaviour; Computing the Capacitances; Propagation Delay: First-Order Analysis; Propagation Delay from a Design Perspective; Power, Energy, and Energy-Delay; Dynamic Power Consumption; Static Consumption; Putting It All Together; Analysing Power Consumption; Technology Scaling and its Impact on the Inverter Metrics.
Unit-3 DESIGNING COMBINATIONAL AND SEQUENTIAL CIRCUITS: Static CMOS Design; Complementary CMOS; Ratioed Logic; Pass-Transistor Logic; Dynamic CMOS Design; How to Choose a Logic Style; Designing Logic for Reduced Supply Voltages. Timing Metrics for Sequential Circuits; Classification of Memory Elements; Static Latches and Registers; The Bistability Principle; Multiplexer-Based Latches; Master-Slave Edge-Triggered Register; Low-Voltage Static Latches; Static SR Flip-Flops—Writing Data by Pure Force; Dynamic Latches and Registers; Dynamic Transmission-Gate Edge-triggered Registers; C2MOS—A Clock-Skew Insensitive Approach; True Single-Phase Clocked Register (TSPCR).
Unit-4 TIMING ISSUES IN DIGITAL CIRCUITS: Timing Classification of Digital Systems; Synchronous Interconnect; Mesochronous interconnect; Plesiochronous Interconnect; Asynchronous Interconnect; Synchronous Design — An In-depth Perspective; Synchronous Timing Basics; Sources of Skew and Jitter; Clock-Distribution Techniques. Latch-Based Clocking, Clocking in IC’s: Basic Concepts PLL and DLL; Building Blocks of a PLL; Future Directions and Perspectives; Distributed Clocking Using DLLs; Synchronous versus Asynchronous Design.
Text Book:
Jan Rabaey, AnanthaChandrakasan, and Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice Hall, 2003.
Reference Books:
N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition, Addison-Wesley, 2005.
D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd edition, McGraw Hill, 2004.
Name of the Centre: CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV 452, Title of the Course: Nano Fabrication Lab
L-T-P: 1-0-7 Credits: 4
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Gain hands on experience and skills in Micro-electronic device processing and clean-room practices involved in Integrated Circuit fabrication industry.
CO-2: Analyze the process protocols/steps followed in IC fabrication technology.
CO-3: Analyze the physical reasons that are limiting the current fabrication
technology and Propose new procedures to overcome these limits.
CO-4: Fabricate and test GaAs based Schottky Diode and MESFET structures.
CO-5: Fabricate and test Si based Schottky Diode and MOS Capacitor.
CO-6: Discuss the role of processing in device functionalities and propose new / alternate device structures / parameters / processes.
CO-7: Communicate the results of all experiments in the form of a written technical report.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
1 |
1 |
2 |
1 |
1 |
0 |
1 |
0 |
3 |
0 |
| CO2 |
3 |
1 |
3 |
2 |
2 |
1 |
0 |
1 |
0 |
3 |
1 |
| CO3 |
3 |
2 |
3 |
3 |
3 |
2 |
0 |
1 |
0 |
3 |
3 |
| CO4 |
3 |
3 |
3 |
3 |
3 |
3 |
0 |
2 |
0 |
3 |
3 |
| CO5 |
3 |
3 |
3 |
3 |
3 |
3 |
0 |
2 |
0 |
3 |
3 |
| CO6 |
3 |
3 |
3 |
3 |
3 |
3 |
0 |
2 |
0 |
3 |
3 |
| CO7 |
2 |
3 |
1 |
1 |
1 |
3 |
0 |
0 |
0 |
2 |
2 |
Detailed Syllabus:
1. Layout Design, Use of design rules, layout design of 1 CMOS circuit
2. Processing introduction: Substrate/wafer scribing/cleaving, Substrate/wafer wafer cleaning, spin-coating, lithography, etch and lift-off process for obtaining patterned deposited layers
3. GaAs processing and lithography: Process steps for GaAs (implanted/multilayer wafer) to pattern for carrier concentration, mobility measurements and optionally FET.
4. Thin film deposition by sputtering, evaporation and spin coating
5. Fabrication of Ohmic contacts, Schottky Diode and MOS Capacitor.
6. Testing.
Text books:
- “Semiconductor Material and Device Characterization” by Dieter K. Schroder (Wiley-IEEE Press; 3 edition (2015))
- “The Science and Engineering of Microelectronic Fabrication” by Stephen A Campbell (Oxford University Press; Second edition (2012))
- “VLSI Technology” by S.M. Sze (McGraw Hill Education; 2 edition (2017))
Name of the Centre: CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV453 Title of the Course: Semester Project-II
L-T-P: 0-0-6 Credits: 3
Prerequisite Course / Knowledge (If any): MV402, MV409 and MV451
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Design of one of the most widely used analog and mixed-signal IC building block such as op-amp, ADC, DAC, PLL, DLL, LNA etc.,.
CO2: Implement the selected building block for manufacturability by performing the checks such as PVT simulations, Monte-Carlo simulation etc.,
CO3: Design and simulate of layout, post-layout simulation, floor-planning etc.,
CO4: Project management, tapeout of the IC in a target technology
CO5: Verify by the building block by test and measurement of the IC
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
3 |
2 |
– |
2 |
2 |
3 |
2 |
3 |
2 |
3 |
| CO2 |
2 |
3 |
2 |
– |
2 |
2 |
2 |
3 |
3 |
2 |
3 |
| CO3 |
2 |
3 |
2 |
– |
2 |
3 |
2 |
3 |
3 |
2 |
3 |
| CO4 |
2 |
3 |
2 |
– |
2 |
3 |
2 |
3 |
3 |
2 |
2 |
| CO5 |
3 |
2 |
3 |
2 |
3 |
2 |
– |
2 |
2 |
3 |
3 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping.
Detailed syllabus:
Project: Design of one of the most widely used analog and mixed-signal IC building block such as op-amp, ADC, DAC, PLL, DLL, LNA. Design starts from specifications, followed simulation at the circuit level and layout level, and ends by test and measurement.
Name of the Centre: CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV454 Title of the Course: Seminar + Comprehensive Viva
L-T-P: 0-0-2 Credits: 2
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO1: demonstrate the ability to perform critical readings.
CO2:demonstrate the ability to evaluate, credit, and synthesize sources.
CO3:demonstrate the ability to collaborate with others as they work on intellectual projects (reading, writing, speaking, researching…).
CO4:demonstrate the ability to speak and articulate on technical subjects.
CO5: demonstrate the ability to prepare technical presentation appropriately and effectively.
CO6:challenge and offer substantive replies to others’ arguments, comments, and questions.
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
1 |
1 |
1 |
|
1 |
|
|
|
|
|
2 |
| CO2 |
2 |
1 |
3 |
|
2 |
|
|
|
|
|
2 |
| CO3 |
3 |
1 |
3 |
|
3 |
|
|
|
|
|
2 |
| CO4 |
1 |
3 |
1 |
|
3 |
3 |
|
|
|
|
2` |
| CO5 |
3 |
1 |
1 |
|
3 |
|
|
|
|
|
2 |
| CO6 |
3 |
1 |
2 |
|
3 |
|
|
|
|
|
2 |
| CO7 |
3 |
1 |
3 |
|
3 |
|
|
|
|
|
2 |
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV501 Title of the Course: Project work+seminar+Dissertation+viva
L-T-P: Credits: 48
Prerequisite Course / Knowledge (If any): First two semester course works
Course Outcomes (COs)
After completion of the first two semester course work each student will do a two-semester project in any area related to their study. After the completion of the one semester of the project work, the students will be able to
CO-1: Carryout literature survey in the field of study
CO2: Define the problem.
CO3: Formulate the objectives and hypothesis.
CO4: Communicate in the form of technical seminar
After the completion of the second semester of the project work, the students will be able to
CO5: Execute the experimental study in order to achieve the defined objectives
CO6: Implement the objective
CO7: Analyse and interpret the results
CO8: Communicate the results of the entire study in the form of technical
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
1 |
1 |
1 |
|
1 |
|
|
|
|
|
2 |
| CO2 |
2 |
1 |
3 |
|
2 |
|
|
|
|
|
2 |
| CO3 |
3 |
1 |
3 |
|
3 |
|
|
|
|
|
2 |
| CO4 |
1 |
3 |
1 |
|
3 |
3 |
|
|
|
|
2` |
| CO5 |
3 |
1 |
1 |
|
3 |
|
|
|
|
|
2 |
| CO6 |
3 |
1 |
2 |
|
3 |
|
|
|
|
|
2 |
| CO7 |
3 |
1 |
3 |
|
3 |
|
|
|
|
|
2 |
| CO8 |
1 |
3 |
1 |
1 |
2 |
3 |
|
|
|
|
2 |
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV461 Title of the Course: VLSI Test and Verification
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): MV451
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Generate test cases for combinational and sequential circuits.
CO2: Implement algorithms for built in self-test.
CO3: Generate automatic test patterns for design for testability and BIST for testing of logic and memories.
CO4: Check combinational equivalence and temporal logics.
CO5: Implement Binary Decision Diagrams (BDDs).
Mapping of Course Outcomes (Cos) with Program Outcomes (Pos)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
3 |
2 |
– |
2 |
2 |
3 |
2 |
2 |
2 |
2 |
| CO2 |
2 |
3 |
2 |
– |
2 |
2 |
3 |
2 |
2 |
2 |
2 |
| CO3 |
2 |
2 |
2 |
3 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
| CO4 |
2 |
3 |
2 |
3 |
3 |
2 |
3 |
3 |
3 |
3 |
3 |
| CO5 |
2 |
2 |
2 |
2 |
3 |
2 |
2 |
3 |
2 |
3 |
3 |
| CO6 |
3 |
2 |
2 |
3 |
2 |
3 |
2 |
2 |
3 |
2 |
2 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
VLSI Testing:
Unit-1: Introduction, Fault models, Fault Simulation, Test generation for combinational circuits, Test generation algorithms for sequential circuits and Built in Self-test.
Unit-2: Automatic test pattern generation. Design for testability. Scan design. Test interface and boundary scan. System testing and test for SOCs. Iddq testing, Delay fault testing. BIST for testing of logic and memories. Test automation.
Verification Techniques:
Unit-3: Introduction to Hardware Verification and methodologies, Binary Decision Diagrams(BDDs) and algorithms over BDDs
Unit-4: Combinational equivalence checking, Temporal Logics, Modeling sequential systems and model checking, Symbolic model checking.
Text Books:
Michael L. Bushnell and Vishwani D. Agrawal, “Essentials of Electronic Testing, for Digital, memory and Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers (2001). ISBN: 0-7923-799-1-8
H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985
References:
M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, IEEE Press, 1994
M. Huth and M. Ryan, Logic in Computer Science, Cambridge Univ. Press, 2004
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV462 Title of the Course: VLSI CAD algorithms
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): IC403 course
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Discuss general sense of foundational algorithms for transforming a structural representation of a VLSI system to layout representation.
CO2: Analyze the layout interms of topological, geometric, timing and power-consumption constraints of the design
CO3: Develop problem formulation skills related to Physical design automation
CO4: Analyze the physical design problems and apply appropriate automation algorithm(s) for partitioning, floor planning, placement and routing
CO5: Evaluate the performance of new optimization algorithms for solving physical design automation problems.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
1 |
1 |
2 |
1 |
3 |
1 |
2 |
2 |
2 |
1 |
3 |
| CO2 |
1 |
1 |
3 |
1 |
3 |
2 |
2 |
2 |
2 |
1 |
2 |
| CO3 |
1 |
2 |
3 |
1 |
3 |
1 |
3 |
3 |
2 |
1 |
3 |
| CO4 |
2 |
2 |
3 |
1 |
2 |
1 |
3 |
2 |
2 |
1 |
2 |
| CO5 |
2 |
2 |
3 |
3 |
3 |
3 |
3 |
2 |
3 |
1 |
3 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed syllabus:
Unit 1: Introduction to Electronic Design Automation (EDA),
Partitioning Algorithms: Kernighan-Lin (KL) Algorithm, Extensions of the Kernighan-Lin Algorithm, Fiduccia-Mattheyses (FM) Algorithm
Unit 2: Floorplanning: Floorplan Representations, normalised polish expression, Cluster Growth, Simulated Annealing algorithm, Integer linear programming.
Unit 3: Placement: Optimization objective, Cos functions and constraints, Mincut algorithm, Simulated annealing algorithm algorithm, Timber wolf algorithm.
Unit 4 Routing:
Global routing: Optimization goal, Terminology and Definitions, Optimization Goals, The Global Routing Flow, Single-Net Routing , Full-Netlist Routing,
Detailed routing: Horizontal and vertical constraint graph, channel routing algorithm (left edge algorithm), switchbox routing, over the cell routing,
Area routing, Non Manhattan routing, Clock tree routing, clock tree synthesis
Unit 5: Timing analysis and performance constraints, Timing driven placement, timing driven routing.
Textbook: S. M. Sait and H. Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific, 1999
References:
- S. K. Lim, Practical Problems in VLSI Physical Design Automation, Springer, 2008
- VLSI Physical Design: From Graph Partitioning to Timing Closure by Andrew B. Kahng , Jens Lienig , Igor L. Markov , Jin Hu , Springer, Dordrecht Publication, 2011
- Algorithms for VLSI Design Automation 1st Edition by Sabih H. Gerez, Wiley publisher, ISBN 13: 978-0471984894
- Related IEEE journal papers
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV463: Title of the course : Special Topics in Analog and Mixed Signal IC Design
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): MV402
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Design of physical interfaces for high-speed data transmission systems
CO-2: Design high-speed serial interfaces and signal integrity as well as high-speed electrical interfaces
CO-3 Design different kinds of A/D and D/A converters using modern system and circuit level design tools
CO-4 Implement Nyquist rate AD converters, over sampled data converters for building high performance data converters
CO-5 Realize top-down Design Approach of a DC-DC Converter Selecting topology
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
2 |
2 |
1 |
1 |
1 |
3 |
2 |
1 |
1 |
1 |
| CO2 |
3 |
2 |
3 |
2 |
2 |
1 |
3 |
2 |
1 |
1 |
1 |
| CO3 |
3 |
2 |
3 |
1 |
2 |
2 |
3 |
3 |
2 |
2 |
3 |
| CO4 |
3 |
2 |
2 |
2 |
2 |
1 |
3 |
3 |
1 |
2 |
3 |
| CO5 |
3 |
2 |
3 |
3 |
3 |
2 |
3 |
2 |
2 |
2 |
2 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus
Unit-1: The design of physical interfaces for high-speed data transmission systems.The course includes lectures introducing to high-speed serial interfaces, lectures on signal integrity as well as high-speed electrical interfaces. Several problems and a design project are presented during in this course and have to be solved as homework.
Unit-2: The basic architectures and design methodologies needed to design different kinds of A/D and D/A converters using modern system and circuit level design tools.An introduction to data converters and lectures on data converter specifications, Nyquist rate DA converters, Nyquist rate AD converters, over sampled data converters as well as on circuits for building data converters.
Unit-3: Introduction to Power Management and Voltage Regulators, Linear Regulators, Switching DC-DC Converters and Control Techniques Types (Buck, boost, buck-boost), Top-down Design Approach of a DC-DC Converter Selecting topology, Introduction to Advanced Topics in Power Management Digitally controlled dc-dc converters
Text book (s): R. Plassche, “Integrated Analog-to-Digital and Digital-to Analog converter,” Kluwer 1994.
– R.Schreier, G.C.Themes, “Understanding Delta-Sigma Data Converters”, Wiley Interscience, 2005.
– Digital Signal Processing, “J.G.Proakis, D.G. Monolakis”, Macmillian Publishing Company, 1992.
– R.J.Baker, “CMOS, Circuit design, Layout and Simulation”, Wiley Interscience, 2005.
– F. Maloberti, “Data Converters,” Springer 2007.
Switch-Mode Power Supplies: SPICE Simulations and Practical Designs by Christophe P. Basso, BPB Publications, 2010
Fundamentals of Power Electronics, 2nd edition by Robert W. Erickson, Dragan Maksimovic, Springer (India) Pvt. Ltd, 2005
Power Management Techniques for Integrated Circuit Design By Ke-Horng Chen, Wiley-Blackwell, 2016
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV464: Title of the course : Wireless Communication IC Design
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): MV402
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Analysis, and design of CMOS Radio frequency (RF) integrated circuits for wireless communication systems
CO-2: Designing RF main blocks such as Low-Noise-Amplifier (LNA), mixer, Voltage-Controlled-Oscillator (VCO), and Phase-Locked-Loop (PLL).
CO-3 Analyze the role of different architectural techniques on target performance indicators
CO-4 Design architectures of RF system and master the keypoint of designing RF circuits
CO-5 Design circuits and do simulation with Cadence SpectreRF during lab time
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
2 |
2 |
1 |
1 |
1 |
3 |
2 |
1 |
1 |
1 |
| CO2 |
3 |
2 |
3 |
2 |
2 |
1 |
3 |
2 |
1 |
2 |
2 |
| CO3 |
3 |
2 |
3 |
1 |
2 |
2 |
3 |
3 |
1 |
2 |
2 |
| CO4 |
3 |
2 |
2 |
2 |
2 |
1 |
3 |
2 |
2 |
2 |
1 |
| CO5 |
3 |
2 |
3 |
3 |
3 |
2 |
3 |
3 |
3 |
3 |
2 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Unit-1
Introduction to RF and Wireless Technology; Basic Concepts in RF Design; Communication Concepts
Unit -II
Transceiver Architectures; Low Noise Amplifiers; Mixers
Unit – III
Passive Devices; Oscillators; Phase-Locked Loops
Unit – IV
Integer-N Frequency Synthesizers; Fractional-N Synthesizers;
Unit – IV
Power Amplifiers; Transceiver Design Example
Text book (s):
Behzad Razavi, RF Microelectronics, Second Edition, Pearson Education India; 2 editions (2013)
Reference materials:
Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Second Edition
ISSCC/CICC/RFIC Symposium Proceedings
Journal of Solid-State Circuits (JSSC)/Transactions on Circuits and Systems I&II (TCAS I&II)
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV465 Title of the Course: VLSI Signal processing
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge : IC403 course
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Explain the methodologies to design custom or semicustom VLSI circuits of DSP algorithms.
CO-2: Apply speed/area/power optimized architectural techniques to DSP algorithms.
CO-3 Analyze the role of different architectural techniques on target performance indicators
CO-4 Design a DSP system using FPGA
CO-5 Create new architecture for different DSP units/subunits
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
2 |
2 |
1 |
1 |
1 |
3 |
2 |
|
|
1 |
| CO2 |
3 |
2 |
3 |
2 |
2 |
1 |
3 |
2 |
|
|
1 |
| CO3 |
3 |
2 |
3 |
1 |
2 |
2 |
3 |
1 |
|
|
2 |
| CO4 |
3 |
2 |
2 |
2 |
2 |
1 |
3 |
1 |
|
|
2 |
| CO5 |
3 |
2 |
3 |
3 |
3 |
2 |
3 |
1 |
|
|
2 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed syllabus
Unit-1
DSP Algorithm Design – DSP Representation (Data-flow, Control-flow, Signal-flow graphs and block diagrams), filter structures, Iteration bound, Longest Path Matrix algorithm,
Unit-II
Circuit and Architecture Design – Hardware design of real and complex multiplication and addition. Pipelining, parallel processing, Retiming
Unit III: Unfolding, Folding, Systolic architecture design, Fast Convolution algorithms
Unit- IV
Algorithm strength reduction in Filters, Bit level arithmetic architectures: bit-parallel, bit-serial Multiplier, Distributed arithmetic architecture,
Unit-V
Speed/area optimized architecture for matrix multiplication, matrix inversion, CORDIC architecture, Speed/area optimized architecture of FFT, redundant number systems, scaling and round off noise, Case study- 1: FPGA of implementation of artificial neural network, case study -2: FPGA implementation of Orthogonal matching Pursuit algorithm,
Books recommended:
- K.K. Parhi – VLSI Digital Signal Processing Systems – Design and Implementation, Wiley publication (2015 reprint)
- Roger Woods, John McAllister, Gaye Lightbody, Ying Yi, FPGA-based implementation of Signal Processing systems, Wiley publication (2008)
References:
- Pramod Kumar Meher, On Efficient Retiming Of Fixed-Point Circuits, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016
- Supriya Aggarwal, Pramod K. Meher, And Kavita Khare Concept, Design, And Implementation Of Reconfigurable CORDIC , IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016
- Lakshmi, B. And Dhar, A. S.CORDIC Architectures: A Survey, VLSI Design, Hindwai, Volume 2010 , Article ID 794891
- IEEE papers related to VLSI signal processing
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV466, Title of the course: Microsystems Modeling and Design
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): MV402 and MV453
Course Outcomes (COs)
After completion of the course, the students will be able to
CO 1: Design bottom-up and top-down design flow
CO 2: Model switched capacitor circuits and phased locked loops
CO 3: Model signal processing problems and RF communication problems in MATLAB
CO 4: Model signal processing problems and RF communication problems by using Simulink tool box.
CO 5: Design system-level framework for and architectural exploration, performance modeling, functional verification, and high-level synthesis.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
2 |
2 |
2 |
1 |
1 |
2 |
3 |
1 |
3 |
3 |
| CO2 |
3 |
3 |
2 |
1 |
2 |
3 |
2 |
3 |
1 |
3 |
2 |
| CO3 |
1 |
3 |
1 |
2 |
3 |
3 |
1 |
2 |
2 |
1 |
1 |
| CO4 |
1 |
3 |
2 |
2 |
1 |
1 |
2 |
2 |
1 |
2 |
3 |
| CO5 |
3 |
3 |
1 |
2 |
3 |
3 |
3 |
1 |
2 |
3 |
3 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Unit-1 Analog Design Flow
· Design Trends
· Design Challenges and Drives
· Bottom-up vs. Top-down
· Discussions
Unit -II Analog modeling language Verilog-AMS
· Modeling Concepts
· Verilog-A Language Overview Describing a System
· Analog Systems
· Nodes
· Conservative Systems
· Signal-Flow Systems
· Mixed Conservative and Signal-Flow Systems
· Simulator Flow
Unit – III Discrete Time Analog Modeling of
· Project 1: Switched Capacitor Circuits
· Project 2: Phased Locked Loops
Unit – IV MATLAB
· Introduction to MATLAB
· Problem Solving by MATLAB
Unit – V Simulink
· Introduction to Simulink
· Modeling Mathematical Functions and Waves
· Waves Modeling Ordinary Differential Equations
· Modeling Difference Equations
· Signal Processing Problems Modeling
· RF and Signal Processing Toolbox
Unit – VI SystemC and SystemC AMS Brief Introduction
· Introduction to SystemC
· System-Level Modeling, and Architectural Exploration,
· Performance Modeling, Functional Verification, and High-Level Synthesis
Text book (s):
- Ken Kundert, “Mixed Signal Design Flow”
- Frevert et al., “Modeling and Simulation for RF, System Design”, Springer, 2006.
- Herve, “VHDL-AMS Anwendungen und IndustriellerEinsatz”, Oldenbourg, Muenchen, 2006.
- Peter Asthenden, “The Designer’s Guide to VHDL”, Morgan Kaufmann Publishers Inc, 2002.
Reference materials
www.systemc-ams.org
www.systemc.org
Name of the Centre :CASEST
Name of the Academic Program M.Tech (MVLSI)
Course Code: MV467: Title of the course: Sensors, Science and Technology
L+T+P (4+0+0)
L-T-P: 4-0-0 Credits: 4
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Understand various types of Sensors & Transducers and their working principle
CO-2: Acquire knowledge on sensors and their suitability in application of measuring different physical quantities and their ranges.
CO-3: Understand the concept of chemical and biosensors, design and fabrication, types and their applications. To explain biosensors and bioelectronics devices
CO-4: Understand the principle of transduction, classifications and the characteristics of different transducers.
CO-5: Design an integrated sensor system with different types of sensors
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
2 |
3 |
1 |
1 |
3 |
|
|
3 |
3 |
|
| CO2 |
3 |
2 |
3 |
1 |
3 |
3 |
|
|
3 |
3 |
|
| CO3 |
3 |
2 |
3 |
1 |
3 |
2 |
|
|
3 |
3 |
|
| CO4 |
3 |
2 |
2 |
1 |
2 |
3 |
|
|
3 |
3 |
|
| CO5 |
3 |
2 |
3 |
2 |
3 |
3 |
|
|
3 |
3 |
|
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Unit-1: Sensor fundamentals: Definition, Importance of sensors, classification of sensors,
Physical sensor design and principles: Flow of sensor design, Principles of sensor design for temperature, Flow, Displacement, Velocity/ Speed, Acceleration, Rotation, Force, Torque, Impact, pressure and Level measurements.
Unit II: Chemical and Biological sensor design and principles: Principles of sensor design for Gas, water quality, pH, moisture, humidity, pesticide residue, explosive, adulteration in oils, body parameters such as blood pressure, glucose, heart rate etc.
Unit- III: Transducers: Classification of Transducers, Different types of transducers such as Electrical Transducers, Resistance Transducers, Variable Inductance Transducers, Capacitive Transducers, Piezoelectric Transducers, Hall Effect Transducers, Thermoelectric Transducers and Photoelectric Transducers.
Unit IV: Remote monitoring of sensors: Principles of data transfer and retrieval
Unit – V: Sensor Applications: Strain gauges, Proximity Sensors, Pneumatic Sensors, Light Sensors, Tactile Sensors, Fiber Optic Transducers, Digital Transducers, Smart devices, wireless sensors, internet of things
Text and reference book (s):
- Measurement systems and sensors by Waldemar Nawrocki.
- Chemical sensors by Robert W Cattrall,
- Sensors and actuators control systems instrumentation by Clarence W. de Silva
- Handbook of chemical and biological sensors Edited by Richard F.Taylor and Jerome S.Schultz
- Fiber optic sensors and introduction to engineers and scientists, Eric Udd
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV468 Title of the Course: Thin Film Technology
L-T-P: 4-0-0 Credits: 4
Prerequisite Course / Knowledge (If any): Nill
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Discuss the mechanism of thin film growth
CO-2: Explain the process for thin film preparation and fabrication
CO-3 Explain different methods of characteristics of thin films
CO-4 Apply the gained knowledge for device fabrication
CO-5 Apply the gained knowledge to design new thin film processes, materials and Devices.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
2 |
3 |
1 |
1 |
3 |
|
|
3 |
3 |
|
| CO2 |
3 |
2 |
3 |
1 |
3 |
3 |
|
|
3 |
3 |
|
| CO3 |
3 |
2 |
3 |
1 |
3 |
2 |
|
|
3 |
3 |
|
| CO4 |
3 |
2 |
2 |
1 |
2 |
3 |
|
|
3 |
3 |
|
| CO5 |
3 |
2 |
3 |
2 |
3 |
3 |
|
|
3 |
3 |
|
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Unit-I: Introduction to thin films: definition, fundamentals of thin film growth on a substrate, basic requirements for thin film preparation, epitaxy, structural and microstructural evolution.
Unit-II : Physical vapour deposition techniques: Need for vacuum in PVD; fundamentals of vacuum technology including pressure measurement and vacuum production; Fundamentals of evaporation and sputtering; description of variants of evaporation such as resistive, electron beam and ion beam assisted. Sub-variants such as reactive evaporation, co-evaporation, and sequential evaporation; description of variants of sputtering such as DC, Magnetron and RF sputtering and the combinations, ion beam sputtering; Sub-variants such as reactive sputtering, co-sputtering and sequential sputtering, bias sputtering. Pulsed laser deposition, Molecular beam epitaxy.
Unit-III: Chemical Vapour deposition: Basics of CVD, reactor design, different gas flow regimes, different precursor types for deposition and selection rules; Different types of CVD such as atmospheric, low pressure, plasma enhanced and Metallo-organic CVD, Atomic layer deposition.
Unit IV: Chemical solution and related techniques: Sol-gel, electrodeposition, spray pyrolysis, spin and dip coating, electroplating etc.
Unit V: Process control and thickness measurement: Quartz crystal monitoring; Residual gas analysis; Reflection High energy electron diffraction (RHEED); optical interferometry, surface profilometry- optical and stylus based.
Applications of thin films in electronics, optics, optoelectronics, magnetism, sensing etc.
Text and reference book (s):
- Handbook of thin film materials, Hari Singh Nalwa.
- Handbook of thin-film deposition processes and techniques principles, methods, equipment and applications Seshan, Krishna,ed
- Thin film materials: stress, defect formation and surface evolution / Ben Freund, Subra Suresh.
- Thin film materials technology sputtering of compound materials / by Kiyotaka Wasa, Makoto Kitabatake, Hideaki Adachi.
- Materials science of thin films: description and structure/ by Milton Ohring
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course No – MV469: Title of the course: Advanced RF Devices and Circuits
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): RF/Microwave ICs Theory and Lab
Course Objectives: This is an advanced course to build up on what students have learned from the course “RF/Microwave ICs Theory & Lab”. In this they will learn the EDA tools that are to be used for dsigning and the numerical methods behind them. They will be learning the design techniques for passive and active high frequency circuits. Recent concepts and techniques like meta materials, magneto electric devices and on wafer probing will be introduced to them.
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Analyze the EDA tools available for high frequency circuit Engineering and difference between circuit theory based CAD and field theory based CAD, nonlinear high frequency circuit analysis as well as available EDA tools.
CO-2: Analyze and design passive high frequency circuits and their design with specific examples.
CO-3 Analyze and design advanced passive high frequency devices that employ non reciprocal magnetic elements, metamaterials, magnetoelectrics and micromachined devices as well as the on wafer probing techniques for their characterization.
CO-4 Analyze and active high frequency circuits and their design with EDA tools including layout with specific examples.
CO-5 Create an active and a passive high frequency circuit using EDA tools. (As a Mini Project).
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
1 |
3 |
3 |
3 |
1 |
0 |
2 |
3 |
0 |
2 |
| CO2 |
3 |
1 |
3 |
3 |
3 |
1 |
0 |
2 |
3 |
0 |
2 |
| CO3 |
3 |
1 |
3 |
3 |
3 |
1 |
0 |
2 |
3 |
0 |
2 |
| CO4 |
3 |
1 |
3 |
3 |
3 |
1 |
0 |
2 |
3 |
0 |
2 |
| CO5 |
3 |
3 |
3 |
3 |
3 |
3 |
0 |
2 |
3 |
0 |
2 |
Detailed Syllabus
Unit-I: EDA tools for MIC/ MMIC Design
Numerical Techniques for the analysis and design of RF/Microwave structures, circuit theory based CAD, field theory based CAD, nonlinear RF and Microwave circuit analysis. Introduction to available EDA tools. Design examples using EDA tools.
Unit-II: Passive device and circuit design -1
Miniaturized Resonators, Varactors, Filters, Phase shifters.
Power dividers and directional couplers: Design of coupled striplines or microstrip lines, Even and odd modes, a quarter-wave coupled line section, multiple section directional couplers, Lange Coupler, T-junction power divider, Wilkinson Power divider.
Unit- III: Passive device and circuit design -2
Non –Reciprocal devices, Magneto Electric devices. Meta material concepts for high frequency passives design, Micromachined passives and their equivalent circuits, On wafer probing and on wafer calibration techniques for miniature devices.
Unit- IV: Active circuit design for RF/Microwave ICs.
Active devices for RF/Microwave ICs. Design of amplifiers, oscillators, mixers and switches. Usage of EDA tools in active circuit design and simulation. Layout generation, simulation and optimization.
Unit-V: Mini projects: On circuit design and simulation (both active and passive ICs) using EDA tools.
Text Books:
David M. Pozar, “Microwave Engineering,” 2nd Edition, John Wiley 1998, ISBN 0-471-17096-8.
Les Besser, Rowan Gilmore, Practical RF circuit design for modern wireless systems: Vol. 1: Passive circuits and systems, Artech House, ISBN-10 1580536751
Les Besser, Rowan Gilmore, Practical RF circuit design for modern wireless systems: Vol. II: Active Passive circuits, Artech House, ISBN-10 9781580535229
Related IEEE Journal Papers.
Reference Books:
K. C. Gupta, Ramesh Garg, InderBahl, and Prakash Bhartia, “Microstrip Lines and Slotlines,” Artech House, 2nd edition, 1996, ISBN: 089006766X.
T. C. Edwards and M. B. Steer, “Foundations of Interconnect and Microstrip Design,” John Wiley & Sons, 3rd edition, 2001, ISBN: 0471607010.
Mike Golio (Ed.), The RF and Microwave Handbook, CRC Press. ISBN: 9780849385926.
Jean-Fu Kiang, Novel technologies for microwave and millimeter-wave applications, Kluwer Academic Publishers. ISBN -10: 1441954015.
I.D. Robertson and S.Lucyszyn, RFIC and MMIC design and technology, , IEE Circuits, Devices and Systems Series 13. ISBN-10 : 0852967861
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course No – MV470: Title of the course: III-V Compound Semiconductors
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): Nil
Course No – MV470: III-V Compound Semiconductors L+T+P (4+0+0)
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Discuss the Physics, properties, preparation, and processing of compound semiconductors
CO-2: Explain the technology of compound semiconductors. process for thin film preparation and fabrication
CO-3 Discuss the theory and practice of heterostructure , quantum structure, metal-semiconductor field effect transistors (MESFETs); heterojunction, field effect transistors (HFETs) and bipolar transistors (HBTs).
CO-4 Apply the gained knowledge for device fabrication
CO-5 Apply the gained knowledge for different applications of compound devices
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
2 |
3 |
1 |
1 |
3 |
|
|
3 |
3 |
|
| CO2 |
3 |
2 |
3 |
1 |
3 |
3 |
|
|
3 |
3 |
|
| CO3 |
3 |
2 |
3 |
1 |
3 |
2 |
|
|
3 |
3 |
|
| CO4 |
3 |
2 |
2 |
1 |
2 |
3 |
|
|
3 |
3 |
|
| CO5 |
3 |
2 |
3 |
2 |
3 |
3 |
|
|
3 |
3 |
|
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping.
Detailed Syllabus:
Unit-1: Compound Semiconductors: The families (III-V’s, II-VI’s, IV-VI’s, IV-IV’s), alloys, Eg vs a; band structures (E vs k; Γ, L, X minima; direct vs. indirect gaps); crystal lattices, electrical properties, optical properties; trends in properties and the periodic table. The useful compounds. Metal-Semiconductor Interfaces (Schottky Barriers): The compound semiconductor surface; Fermi level pinning. Theories of barrier formation and of current flow; diffusive vs. ballistic flow; contrasts with p-n diodes. Theory and practice of ohmic contacts.
Unit-II: Heterostructures and Heterojunctions: E-x Profiles: ΔEc, ΔEv, Ec(x), Ev(x); no(x), po(x); modulation doping. Conduction parallel to heterojunction; mobility in semiconductors and carrier scattering mechanisms. Heterojunctions: Conduction normal to junction: I-V models and characteristics. Theory of graded layers; creation of internal carrier-specific fields.Coupled quantum structures: super lattices. Resonant tunneling: RTD structure and concept. I-V theory. Related devices and applications: RTD-load logic, memory cells.
Unit III: MESFETs: Basic concept, models for terminal characteristics; accounting for velocity saturation. Dynamic models: large signal switching transients; small signal, high f models. Fabrication sequences; application-specific designs (power, digital, low noise microwave)
Unit IV: HFETs (Doped Channel): Concept; I-V model including velocity saturation; gate 2 characteristics; output conductance; applications of strained layers. HFETs (Intrinsic Gate): HIGFET’s — basic device, features, theory. Complementary structures for logic. HFETs (Modulation Doped): MODFETs — basic device, theory. Deep level problem (transconductance collapse); pseudomorphic solution. Telecommunications applications — key features: gain, bandwidth, linearly, noise.
Unit V: HBTs: Concept: emitter efficiency, base transport, base resistance, junction capacitance. HJ collector and collector-up refinements. Applications of graded layers: control of HJ spikes; ballistic injection; problems with upper-valley minima; State-of-the-art commercial HBT technologies (III-V and IV-IV).
Text book (s):
- Adachi, Sadao. Physical Properties of III-V Semiconductor Compounds: InP, InAs, GaAs, GaP, InGaAs, and InGaAsP. New York, NY: John Wiley & Sons, 1992. ISBN: 0471573299.
- Hess, K. “Diffusive Transport and Thermionic Emission: Appendix G.” In Advanced Theory of Semiconductor Devices. New York, NY: Prentice-Hall, 1988. ISBN: 0780334795.
Reference materials
- Garcia, J. Ch. “Potential Prospects of CBE Technology Compared to MBE as Production Tool for Microwave Devices.” Journal of Crystal Growth188 (1998): 343-348
- Fitzgerald, E. A. “Dislocation in Strained-layer Epitaxy: Theory, Experiment, and Applications.” Materials Science Reports 7 (1991): 87-142.
- Mohammad, S. N., and H. Morkoc. “Progress and Prospects of Group-III Nitride Semiconductors.” Progress in Quantum Electronics 20 (1996): 361-525.
- Bollaert, S., Y. Cordier, M. Zaknoune, T. Parenty, H. Happy, and A. Cappy. “HEMT’s Capability for Millimeter-wave Applications.” Annals of Telecommunications 56 (2001): 15-26.
- Van Hove, M., J. Finders, K. van der Zanden, W. De Raedt, M. Van Rossum, Y. Baeyens, D. Schreurs, and R. Menozzi. “Material and Process Related Limitations of InP HEMT Performance.” Materials Science and Engineering B B44 (1997): 311-315.
- Leyronas, X. and M. Combescot. “Quantum Wells, Wires, and Dots with Finite Barrier: Analytical Expressions for Bound States.” Solid State Comm119 (2001): 631-635.
- Houston, P. A.. “High-frequency Heterojunction Bipolar Transistor Device Design and Technology.” Electronics and Communication Engineering Journal 12 (October 2000): 220-228.
- Delage, S. L. “Heterojunction Bipolar Transistors for Millimeter Waves Applications: Trends and Achievements.” Annals of Telecommunications 56 (2001): 5-14.
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV471 Title of the Course: Nano Technology
L-T-P: 4-0-0 Credits: 4
Prerequisite Course / Knowledge (If any): Nill
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Discuss the size effects on physical and chemical properties of materials
CO-2: Explain the synthesis and processing of nano materials
CO-3 Explain the different methods of characterization of nano materials
CO-4 Explain different fabrication techniques for nano electronics and other devices
CO-5 Apply the general knowledge to design new functional nano materials and devices.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
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3 |
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3 |
1 |
1 |
3 |
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3 |
3 |
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| CO2 |
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3 |
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3 |
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3 |
2 |
3 |
2 |
3 |
3 |
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3 |
3 |
|
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Unit-1 Finite size effects on physical properties of materials: Fundamentals of quantum mechanics of nanoscale systems; Effect of dimensionality on optical, mechanical, electronic and magnetic properties.
Unit -2: Techniques of imaging nanomaterials: Different types of electron microscopy; Scanning probe microscopy; Scanning near field optical microscopy.
Unit 3: Synthesis of nanomaterials by chemical routes: Hydrothermal synthesis, Vapour-liquid-solid synthesis, self assembly techniques, solution based techniques, Atomic layer deposition, Inert gas condensation and electrodeposition.
Unit 4: Fabrication of nanomaterials by physical methods: Electron beam writing, nanoimprint technology, Focused ion beam and other ion beam based technologies, Vapour deposition. Device fabrication: Top down and bottom up approaches such as electron beam and x-ray lithography, self organization, laser based techniques .
Unit 5: Examples of nanoscale materials and applications : Nanowires, nannorods, grapheme and 0-2D materials. Applications: sensors, catalysts, memories, theranostics, nanoelectronic devices such as resonant tunneling diodes and transistors, nanoelectromechanical systems.
Text and reference Books
- Nano electronics and nanosystems by K.Goser
- Nano technology in material science by S. Mitura
- Springer handbook of nano technology edited by Bharat Bhushan
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics and VLSI Design)
Course Code: MV472 Title of the Course: MEMS and THz Technology
L-T-P: 3-1-0 Credits: 4
Prerequisite Course / Knowledge (If any): B.Tech or M.Sc in an area related to Electronics or Physics.
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Analyze the emergent technologies for MEMS as well as THz technology and evaluate the need and relevance of these technologies in emerging Communication technologies.
CO-2: Analyze why micromachining is important for sensors and the issues involved in their design, fabrication and signal transduction.
CO-3 Evaluate the Bulk and Surface micromachining technologies and applicability of Micromachining in the high frequency Electronics.
CO-4 Explain the THz frequency range, the difficulties in using this part of the spectrum and the solutions available as well as emerging, to overcome these difficulties.
CO-5 Apply the technologies, devices and circuits using semiconductors that are available or emerging to realize communication in THz range of frequencies.
CO-6 Evaluate the importance of MEMS and THz technologies in emerging security and communication technologies.
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
2 |
3 |
3 |
3 |
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3 |
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1 |
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1 |
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3 |
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3 |
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1 |
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3 |
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3 |
3 |
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1 |
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1 |
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3 |
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3 |
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3 |
3 |
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3 |
1 |
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3 |
1 |
3 |
Detailed Syllabus
Unit -1
Micromachining vs. Microelectronics, Micromachining and Electronics. Microsystems, Scaling laws
Unit -II
MEMS and Sensors, Silicon and other substrates for MEMS. Micromachining processes.
Signal transduction methods, MEMS IN RF Electronics. MEMS Design and packaging.
Unit- III
THz range of em spectrum. Atmospheric propagation characteristics of THz radiation.
Why THz in Electronics? Active devices for THz operation. Passive devices for THz operation.
Materials for THz technology.
Unit- IV
Surface Integrated Waveguides and micromachined components for THz operation. THz circuits for communication. THz for security applications. Design and simulation of THz circuits.
Unit –V Assignment: What is the circuitry required to use a particular commercial MEMS device in an application?
References:
1. Microsystem Design by Stephen D Seturia, Springer, ISBN-10 : 9788181285461
2. MEMS & Microsystems design and Manufacture, Tai-Ran Hsu, McGraw Hill Education, ISBN 10- 007048709X
3. Semiconductor Terahertz technology: Devices and Systems at Room Temperature Operation. By Guillermo Carpintero et.al, IEEE Press., ISBN -13: 978-1118920428
Name of the Centre :CASEST
Name of the Academic Program M.Tech (Microelectronics & VLSI Design)
Course Code: MV473 Title of the Course: Optoelectronics
L-T-P: 4-0-0 Credits: 4
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Discuss the principle of various integrated optoelectronic devices such as sources, detectors
CO-2: Explain various technology for designing optoelectronic devices and photonic circuits and optoelectronic ICs
CO-3. Discuss various technology for designing optical modulators and waveguide
CO-4 Design optoelectronic systems for different electronic applications
CO-5 Apply the design concepts to realize new optical interconnects
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
2 |
2 |
1 |
1 |
1 |
3 |
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3 |
3 |
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1 |
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1 |
3 |
3 |
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3 |
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1 |
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1 |
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2 |
3 |
3 |
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Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping
Detailed Syllabus:
Unit-1: Light Emission and Absorption : Basic Theory, Direct vs Indirect band gap semiconductor, Band to band and band to impurity transitions. Light Emitting Diodes: LED Structure, materials and characteristics, Light extraction, current spreading, photon recycling, Applications in displays and illumination — considerations, current practice, recent commercial developments
Unit-II Laser Diodes: Feedback and stimulated emission. Cavity design; double hetero structure concept. Quantum well, wire, dot active regions. Strained layers; pseudomorphic active regions.In-plane lasers: double hetero-structure, quantum well, multi-contact, surface emitting. Vertical cavity surface emitting lasers (VCSELs). Modulation and control of emission. New structures and material systems including blue-green lasers and cascade lasers.
Unit-III Detectors: Structure and theory of basic types: p-i-n (conventional and unicarrier), APD, Schottky diode, resonant cavity concepts, Vertical vs. in-plane geometries. Quantum well, inter-subband photodetectors.
Unit IV: Optical Modulators, Multiple quantum well structures, quantum confined Stark effect; SEED. Waveguide couplers, switches, modulators Dielectric Waveguides / Photonic Crystals: Basics of optical cavities and waveguides, Photonic crystal concepts, structures, issues.
Unit V: Photonic Circuits, Optoelectronic Integrated Circuits (OEICs): Integration goals and challenges; applications; Approaches to integration and current state-of-the-art. Epitaxial stacks, multiple-epitaxial runs, epitaxy on processed electronics (GaAs-on-Si, GaAs-on-GaAs, Si-on-GaAs). Bonding, Hybrid integration, Self-assembly.
Quantum Effect Devices: Electron waveguides, single electron transistors, etc.
Text book (s):
- Coldren, L. A., and S. W. Corzine. Diode Lasers and Photonic Integrated Circuits. New York, NY: Wiley Interscience, 1995. ISBN: 0471118753.
- Roencher, E., and B. Vorge. Optoelectronics. Cambridge, UK: Cambridge University Press, 2002. ISBN: 0521778131.
- Chang, Shun Lien. Physics of Optoelectronic Devices. New York, NY: John Wiley, 1995. ISBN: 0471109398.
- Bhattacharya, Pallab. Semiconductor Optoelectronic Devices. 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 1997. ISBN: 0134956567.
- Bergh, A. A. Light Emitting Diodes. Oxford, UK: Clarendon Press, 1976. ISBN: 0198593171.
- Gillesen, K., and W. Schairer. Light Emitting Diodes: An Introduction. Upper Saddle River, NJ: Prentice-Hall, 1987, ISBN: 0135365333.
- Schubert, E. F. Light Emitting Diodes. Cambidge, UK: Cambridge University Press, 2003. ISBN: 0521533511.
Reference materials:
- Forchel, A., M. Kamp, Reithmaier, et al. “Photonic Crystals for Optoelectronic Devices.” In Physics and Simulation of Optoelectronic Devices IX. Edited by Yasuhiko Arakawa, Peter Blood, and Marek Osinski. ISBN: 0819439614. Proceedings of the SPIE 4283 (2001): 406-414.
- Krauss, T. F., and R. M. De La Rue. “Photonic Crystals in the Optical Regime – Past, Present, and Future.” Progress in Quantum Electronics 23 (1999): 51-59.
- Yablonovitch, E. “Inhibited Spontaneous Emission in Solid-State Physics and Electronics.” Physical Review Lett 58 (1987): 2059-2062.
- Delbeke, D., et al. “High Efficiency Semiconductor Resonant-cavity Light-emitting diodes: A Review.” IEEE J on Selected Topics on Quantum Electronics 8 (2002): 189-206.
- Mukai, T. “Recent Progress in Group-III Nitride Light-emitting Diodes.” IEEE J on Selected Topics on Quantum Electronics 8 (2002): 264-270.
- Steigerwald, D. A., et al. “Illumination with Solid State Lighting Technology.” IEEE J on Selected Topics on Quantum Electronics 8 (2002): 310-320.
- Muthu, S., et al. “Red, Green, and Blue LEDs for White Light Illumination.” IEEE J on Selected Topics on Quantum Electronics 8 (2002): 333-338.
- Iga, K. “Vertical-Cavity Surface-Emitting Laser – Progress and Prospects.” IEICE Trans Electron E85-C, no. 1 (2002): 10-20.
- Chang, C. H., L. Chrostowski, and C. J. Chang-Hasnain. “Parasitics and Design Considerations on Oxide-Implant VCSELs.” IEEE Photonics Technology Letters 13, no. 12 (2001): 1274-1276
Name of the Centre :CASEST
Name of the Academic Program M.Tech (MVLSI)
Course Code: MV474 Title of the Course: High Speed VLSI and System on Chip: Design and Implementation
L-T-P: 2-0-4 Credits: 4
Prerequisite Course / Knowledge (If any): Nil
Course Outcomes (COs)
After completion of this course successfully, the students will be able to
CO-1: Describe the System on Chip design flow and requirements (Understand)
CO-2: Explain the concepts of processor architecture and memory design and Interconnects (Understand)
CO-3 Explain the control datapath extraction in any given VLSI system (Understand)
CO-4 Identify the steps involved in validation and verification flow (Analyze)
CO-5 Develop algorithms for the triggering at Large Hardon Collider experiments (Create)
CO-6 Communicate the results of all experiments in the form of written technical report
Mapping of Course Outcomes (COs) with Program Outcomes (POs)
and Program Specific Outcomes (PSOs)
| |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PSO1 |
PSO2 |
PSO3 |
PSO4 |
PSO5 |
| CO1 |
3 |
2 |
1 |
1 |
1 |
2 |
3 |
3 |
1 |
1 |
2 |
| CO2 |
3 |
3 |
3 |
1 |
3 |
3 |
2 |
3 |
1 |
1 |
2 |
| CO3 |
1 |
3 |
3 |
1 |
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2 |
3 |
1 |
1 |
1 |
1 |
| CO4 |
1 |
3 |
2 |
1 |
2 |
3 |
3 |
1 |
1 |
1 |
1 |
| CO5 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
1 |
1 |
3 |
| CO6 |
1 |
3 |
1 |
1 |
1 |
3 |
1 |
1 |
1 |
1 |
1 |
Note: ‘3’ in the box for ‘High-level’ mapping, 2 for ‘Medium-level’ mapping, 1 for ‘Low’-level’ mapping.
Detailed Syllabus:
Unit I: System on Chip design flow, System on Chip design requirements
Unit II: Processors: Processor Selection for SOC, Basic Concepts in Processor Architecture, buffers and branches, VLIW and superscalar processor architectures, Memory design: Cache, DRAM , Interconnects, DMA controller, hardware accelerator
Unit III: High level Synthesis and its Applications : High-Level synthesis benefits, basics, understanding of HLS, C test bench, Linear Algebra library functions, DSP library functions, C++ arbitrary precision types, data-types for efficient hardware
Experiments in Lab:
HLS design analysis
optimization and perform RTL verification
Case study of trigger algorithms developed for the LHC experiments.
Text books:
- Computer System Design System-on-Chip Michael J. Flynn Wayne Luk,published by Published by John Wiley & Sons (2011), ISBN 978-0-470-64336-5
- The Zynq Book, “Embedded Processing with the ARM® Cortex®-A9 on the Xilinx® Zynq®-7000 All Programmable SoC “, by Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, Robert W. Stewart (Chapter 13 and 14)
- Vivado Design Suite User Guide: High‐Level Synthesis (UG902)
